HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 236

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

7.3.4
The UMCLKC bit of memory clock control register (MCCR) should be set to 1 when I bus master
module such as DMAC accesses this memory in sleep mode.
There is the following restrictions when the U memory is accessed in the processing the exception
handling and interrupt while this function is used.
1. The program of the exception handling and the interrupt processing should not be placed in the
2. Eight NOP instructions should be added to the head of the exception handling and the interrupt
3. When the SLEEP instruction is executed, 16 instructions which include above-mentioned eight
• Example 1
• Example 2
Rev. 1.00, 02/04, page 198 of 804
U memory and X/Y memory.
processing program.
NOP instructions for the head of the exception handling and the interrupt processing should be
placed outside of cache (Miss hit or non-cacheable area (P2) ).
Take out outside cache by using the address-array write (associative operation).
(Refer to section 5.4, Memory Mapped Cache in section 5, Cache and Invalidating Specific
Entries in section 5.4.3, Usage Examples.)
The value of vector base register (VBR) is changed to non-cacheable area (P2) before the
SLEEP instruction is executed. In this case, execute the SLEEP instruction after confirming
the written VBR value (the branch instruction for the flag confirmation is used). After SLEEP
ends, the VBR should be restored with the previous value.
sleep mode