HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 25

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 9.28 Burst ROM Access (Data Bus Width 8 Bits, 4-byte Transfer (number of burst 4),
Figure 9.29 Byte-Selection SRAM Basic Access Timing (BAS = 0)......................................... 288
Figure 9.30 Byte-Selection RAM Basic Access Timing (BAS = 1)........................................... 289
Figure 9.31 Example of Connection with 16-Bit Data-Width Byte-Selection SRAM ............... 289
Figure 9.32 Waveform in the Event of a Problem ...................................................................... 290
Figure 9.33 Bus Arbitration Timing (Master Mode) .................................................................. 293
Figure 9.34 Master and Slave Connection Example................................................................... 294
Section 10 Direct Memory Access Controller (DMAC)
Figure 10.1 Block Diagram of the DMAC ................................................................................. 298
Figure 10.2 DMA Transfer Flowchart ........................................................................................ 314
Figure 10.3 Round-Robin Mode................................................................................................. 319
Figure 10.4 Changes in Channel Priority in Round-Robin Mode............................................... 320
Figure 10.5 Data Flow of Dual Address Mode........................................................................... 322
Figure 10.6 Example of DMA Transfer Timing in Dual Mode
Figure 10.7 Data Flow in Single Address Mode......................................................................... 324
Figure 10.8 Example of DMA Transfer Timing in Single Address Mode.................................. 324
Figure 10.9 DMA Transfer Example in the Cycle-Steal Normal Mode
Figure 10.10 Example of DMA Transfer in Cycle Steal Intermittent Mode
Figure 10.11 DMA Transfer Example in the Burst Mode
Figure 10.12 Bus State when Multiple Channels Are Operating................................................ 328
Figure 10.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection............ 329
Figure 10.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection........... 329
Figure 10.15 Example of DREQ Input Detection in Burst Mode Edge Detection ..................... 329
Figure 10.16 Example of DREQ Input Detection in Burst Mode Level Detection .................... 330
Figure 10.17 Example of DMA Transfer End Signal Timing in Cycle Steel Mode Level
Figure 10.18 BSC Ordinary Memory Access
Section 11 Clock Pulse Generator (CPG)
Figure 11.1 Block Diagram of Clock Pulse Generator ............................................................... 334
Figure 11.2 Note on Using a Crystal Resonator ......................................................................... 344
Figure 11.3 Note on Using a PLL Oscillator Circuit .................................................................. 345
Section 12 Watchdog Timer (WDT)
Figure 12.1 Block Diagram of the WDT .................................................................................... 348
Figure 12.2 Writing to WTCNT and WTCSR............................................................................ 352
Access Wait for the 1st time 2, Access Wait for 2nd Time and after 1).................. 286
(Source: Ordinary memory, Destination: Ordinary memory).................................. 323
(Dual Address, DREQ Low Level Detection) ......................................................... 325
(Dual address, DREQ low level detection) ............................................................ 326
(Dual Address, DREQ low level detection)........................................................... 326
Detection ............................................................................................................... 330
(No wait, Idle Cycle 1, Longword Access to 16-bit Device)................................. 331
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