HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 363

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Bus Modes: There are two bus modes: cycle steal and burst. Select the mode in the TB bits of the
channel control register (CHCR).
1. Cycle-Steal Mode
• Normal mode
Figure 10.9 shows an example of DMA transfer timing in the cycle steal mode. Transfer
conditions shown in the figure are:
1. Dual address mode
2. DREQ low level detection
• Intermittent Mode 16 and Intermittent Mode 64
Figure 10.10 shows an example of DMA transfer timing in cycle steal intermittent mode. Transfer
conditions shown in the figure are:
In the normal mode of cycle-steal, the bus mastership is given to another bus master after a
one-transfer-unit (byte, word, long-word, or 16 bytes unit) DMA transfer. When another
transfer request occurs, the bus masterships are obtained from the other bus master and a
transfer is performed for one transfer unit. When that transfer ends, the bus mastership is
passed to the other bus master. This is repeated until the transfer end conditions are satisfied.
In the cycle-steal mode, transfer areas are not affected regardless of settings of the transfer
request source, transfer source, and transfer destination.
In the intermittent mode of cycle steal, DMAC returns the bus mastership to other bus master
whenever a unit of transfer (byte, word, longword, or 16 bytes) is complete. If the next transfer
request occurs after that, DMAC gets the bus mastership from other bus master after waiting
for 16 or 64 clocks in Bφ count. DMAC then transfers data of one unit and returns the bus
mastership to other bus master. These operations are repeated until the transfer end condition is
satisfied. It is thus possible to make lower the ratio of bus occupation by DMA transfer than
the normal mode of cycle steal.
When DMAC gets again the bus mastership, DMA transfer can be postponed in case of entry
updating due to cache miss.
This intermittent mode can be used for all transfer section; transfer requester, source, and
destination. The bus modes, however, must be cycle steal mode in all channels.
Figure 10.9 DMA Transfer Example in the Cycle-Steal Normal Mode (Dual Address,
Bus cycle
DREQ
CPU
CPU
DREQ Low Level Detection)
CPU
DMAC DMAC
Read
Bus mastership returned to CPU once
Write
CPU DMAC DMAC CPU
Read
Rev. 1.00, 02/04, page 325 of 804
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