HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 601

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

20.3.3
IER0 enables the interrupt requests of IFR0. When an interrupt flag is set to 1 while the
corresponding bit of each interrupt enable bit of IFR0 is set to 1, the INT0N or INT1N pin set in
the interrupt select register (ISR0) is asserted low and an interrupt request is issued.
Bit
31
30
29
28
27
26
25
24
Bit Name

BRST IE
SETUP TS IE 0

VBUSF IE

SURES IE
CFDN IE
Interrupt Enable Register 0 (IER0)
Initial
Value
0
0
0
0
0
0
0
R/W
R
R/W
R/W
R
R/W
R
R/W
R/W
CFDN Interrupt Enable
Description
Reserved
This bit is always read as 0. The write value should
always be 0. If 1 is written to this bit, correct operation
cannot be guaranteed.
BRST Interrupt Enable
0: Disables a BRST (bus reset) interrupt request
1: Enables a BRST (bus reset) interrupt request
SETUP TS Interrupt Enable
0: Disables a SETUP TS (setup data receive complete)
1: Enables a SETUP TS (setup data receive complete)
Reserved
This bit is always read as 0. The write value should
always be 0. If 1 is written to this bit, correct operation
cannot be guaranteed.
VBUSF Interrupt Enable
0: Disables a VBUSF interrupt request
1: Enables a VBUSF interrupt request
Reserved
This bit is always read as 0. The write value should
always be 0. If 1 is written to this bit, correct operation
cannot be guaranteed.
SURES Interrupt Enable
0: Disables a SURES interrupt request
1: Enables a SURES interrupt request
0: Disables a CFDN interrupt request
1: Enables a CFDN interrupt request
interrupt request
interrupt request
Rev. 1.00, 02/04, page 563 of 804