HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 18

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

20.4 Operation .......................................................................................................................... 586
20.5 Processing of USB Standard Commands and Class/Vendor Commands ......................... 601
20.6 Stall Operations................................................................................................................. 602
20.7 Example of External Circuitry for USB Function Controller ........................................... 605
20.8 Usage Notes ...................................................................................................................... 606
Rev. 1.00, 02/04, page xviii of xxxviii
20.3.7 EP1 Data Register (EPDR1) ................................................................................ 567
20.3.8 EP2i Data Register (EPDR2i).............................................................................. 568
20.3.9 EP2o Data Register (EPDR2o) ............................................................................ 568
20.3.10 EP3i Data Register (EPDR3i).............................................................................. 568
20.3.11 EP3o Data Register (EPDR3o) ............................................................................ 569
20.3.12 EP4 Data Register (EPDR4) ................................................................................ 569
20.3.13 EP5 Data Register (EPDR5) ................................................................................ 569
20.3.14 EP6 Data Register (EPDR6) ................................................................................ 570
20.3.15 EP0o Receive Data Size Register (EPSZ0o) ....................................................... 570
20.3.16 EP2o Receive Data Size Register (EPSZ2o) ....................................................... 570
20.3.17 EP3o Receive Data Size Register (EPSZ3o) ....................................................... 570
20.3.18 EP6 Receive Data Size Register (EPSZ6) ........................................................... 571
20.3.19 Trigger Register (TRG) ....................................................................................... 571
20.3.20 Data Status Register (DASTS)............................................................................. 572
20.3.21 FIFO Clear Register (FCLR) ............................................................................... 572
20.3.22 DMA Transfer Setting Register (DMA) .............................................................. 573
20.3.23 Endpoint Stall Register (EPSTL)......................................................................... 574
20.3.24 Configuration Value Register (CVR) .................................................................. 575
20.3.25 Time Stamp Register (TSR) ................................................................................ 576
20.3.26 Control Register (CLTR) ..................................................................................... 576
20.3.27 Endpoint Information Register (EPIRn0 to EPIRn5)........................................... 578
20.4.1 Cable Connection................................................................................................. 586
20.4.2 Cable Disconnection ............................................................................................ 587
20.4.3 Control Transfer................................................................................................... 587
20.4.4 EP1, 4 Interrupt-In Transfer................................................................................. 593
20.4.5 EP2i, 5 Bulk-In Transfer (Dual FIFOs) ............................................................... 594
20.4.6 EP2o, 6 Bulk-Out Transfer (Dual FIFOs)............................................................ 595
20.4.7 EP3i Isochronous-In Transfer .............................................................................. 597
20.4.8 EP3o Isochronous Out Transfer........................................................................... 599
20.5.1 Processing of Commands Transmitted by Control Transfer................................ 601
20.6.1 Overview ............................................................................................................. 602
20.6.2 Forcible Stall by Application ............................................................................... 602
20.6.3 Automatic Stall by USB Function Module .......................................................... 604
20.8.1 Setup Data Reception .......................................................................................... 606
20.8.2 FIFO Clear........................................................................................................... 606
20.8.3 Overreading/Overwriting of Data Register.......................................................... 606
20.8.4 Assigning EP0 Interrupt Sources ......................................................................... 607
20.8.5 FIFO Clear when DMA Transfer is Set ............................................................... 607