HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 389

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

12.2.3
The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are
more difficult to write to than other registers. The procedures for reading writing to these registers
are given below.
Writing to WTCNT and WTCSR: These registers must be written by a word transfer
instruction. They cannot be written by a byte or longword transfer instruction. When writing to
WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in
figure 12.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as
the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR.
Bit
2
1
0
WTCNT write
WTCSR write
Address: H'A415FF84
Address: H'A415FF86
Notes on Register Access
Bit Name
CKS2
CKS1
CKS0
Initial
Value
0
0
0
Figure 12.2 Writing to WTCNT and WTCSR
15
15
R/W
R/W
R/W
R/W
H'5A
H'A5
Description
Clock Select
These bits select the clock to be used for the WTCNT
count from the eight types obtainable by dividing the
peripheral clock. The overflow period that is shown
inside the parenthesis in the table is the value when
the peripheral clock (Pφ) is 15 MHz.
Bits 2 to 0 Clock Ratio
000
001
010
011
100
101
110
111
Note:
WDT is running, the up-count may not be performed
correctly. Ensure that these bits are modified only
when the WDT is not running.
If bits CKS2 to CKS0 are modified when the
1
1/4
1/16
1/32
1/64
1/256
1/1024
1/4096
8
8
7
7
Rev. 1.00, 02/04, page 351 of 804
Write data
Write data
Overflow Cycle
(17 us)
(68 us)
(273 us)
(546 us)
(1.09 ms)
(4.36 ms)
(17.48 ms)
(69.91 ms)
0
0