HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 436

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Rev. 1.00, 02/04, page 398 of 804
Bit
3
2
1
Bit Name
TFOVF
TFUDF
RFUDF
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
Transmit FIFO Overflow
0: No transmit FIFO overflow
1: Transmit FIFO overflow
A transmit FIFO overflow means that there has been an
attempt to write to SITDR when the transmit FIFO is full.
When a transmit FIFO overflow occurs, the SIOF
indicates overflow, and writing is invalid.
•
•
•
Transmit FIFO Underflow
0: No transmit FIFO underflow
1: Transmit FIFO underflow
A transmit FIFO underflow means that loading for
transmission has occurred when the transmit FIFO is
empty.
When a transmit FIFO underflow occurs, the SIOF
repeatedly sends the previous transmit data.
•
•
•
Receive FIFO Underflow
0: No receive FIFO underflow
1: Receive FIFO underflow
A receive FIFO underflow means that reading of SIRDR
has occurred when the receive FIFO is empty.
When a receive FIFO underflow occurs, the value of data
read from SIRDR is not guaranteed.
•
•
•
This bit is valid when the TXE bit in SICTR is 1.
When 1 is written to this bit, the contents are cleared.
Writing 0 to this bit is invalid.
If the issue of interrupts by this bit is enabled, an
SIOF interrupt is issued.
This bit is valid when the TXE bit in SICTR is 1.
When 1 is written to this bit, the contents are cleared.
Writing 0 to this bit is invalid.
If the issue of interrupts by this bit is enabled, an
SIOF interrupt is issued.
This bit is valid when the RXE bit in SICTR is 1.
When 1 is written to this bit, the contents are cleared.
Writing 0 to this bit is invalid.
If the issue of interrupts by this bit is enabled, an
SIOF interrupt is issued.