HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 704

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Rev. 1.00, 02/04, page 666 of 804
Bit
9, 8
7
6
5, 4
3
2, 1
0
Bit Name

DBEB
PCBB

SEQ

ETBE
Initial
Value R/W
All 0
0
0
All 0
0
All 0
0
R
R/W
R/W
R
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0. If 1 is written to these bits, correct operation
cannot be guaranteed.
Data Break Enable B
Selects whether or not the data bus condition is included in
the break condition of channel B.
0: No data bus condition is included in the condition of
1: The data bus condition is included in the condition of
PC Break Select B
Selects the break timing of the instruction fetch cycle for
channel B as before or after instruction execution.
0: PC break of channel B is set before instruction execution
1: PC break of channel B is set after instruction execution
Reserved
These bits are always read as 0. The write value should
always be 0. If 1 is written to these bits, correct operation
cannot be guaranteed.
Sequence Condition Select
Selects two conditions of channels A and B as independent
or sequential conditions.
0: Channels A and B are compared under independent
1: Channels A and B are compared under sequential
Reserved
These bits are always read as 0. The write value should
always be 0. If 1 is written to these bits, correct operation
cannot be guaranteed.
Number of Execution Times Break Enable
Enables the execution-times break condition only on
channel B. If this bit is 1 (break enable), a user break is
issued when the number of break conditions matches with
the number of execution times that is specified by BETR.
0: The execution-times break condition is disabled on
1: The execution-times break condition is enabled on
conditions
conditions (channel A, then channel B)
channel B
channel B
channel B
channel B