HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 328

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Byte-Selection SRAM Interface Restrictions:
The BAS bit should not be set to 1 for the byte-selection SRAM while the SDRAM in auto-refresh
is used. If the BAS bit is set to 1, a refresh cannot be issued.
Problems:
When the byte-selection SRAM is accessed (BAS = 1) before a refresh is carried out, the ACTV
command is issued instead of the RD/WR low output during the PALL command cycle.
Therefore, the operation of SDRAM cannot be guaranteed in subsequent REF command.
Avoidance measures:
1. A pseudo SRAM which is mixed with SDRAM should support UB and LB control write.
2. When the WE pin of MCP is necessary to be connected to the RD/WR pin of this LSI to use
When a write access to a flash memory ends, set the UB and LB control (BAS = 0) and then clear
the self-refresh function.
Rev. 1.00, 02/04, page 290 of 804
Make SDRAM enter in self-refresh
Set the functions of CSnBCR and CSnWCR in the flash memory area for using the byte-
Start write access to a flash memory
MCP incorporating a flash memory, make access according to the following procedure.
selection SRAM (BAS = 1): accessing byte-selection SRAM and WE write control.
RD/WR
CKIO
CAS
RAS
CS3
Figure 9.32 Waveform in the Event of a Problem
Instead of the PALL command, the ACTV command is
issued at the first cycle of the refresh sequence.
Low is not output.