HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 418

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

14.4.3
The TMU produces underflow interrupts for each channel. When the interrupt request flag and
interrupt enable bit are both set to 1, the interrupt is requested. Codes are set in the interrupt event
register 2 (INTEVT2) for these interrupts and interrupt processing occurs according to the codes.
The relative priorities of channels can be changed using the interrupt controller (see section 4,
Exception Handling, and section 8, Interrupt Controller (INTC)). Table 14.1 lists TMU interrupt
sources.
Table 14.1 TMU Interrupt Sources
14.5
Writing to Registers: Synchronization processing is not performed for timer counting during
register writes. When writing to registers, always clear the appropriate start bits for the channel
(STR2 to STR0) in the timer start register (TSTR) to halt timer counting.
Reading Registers: Synchronization processing is performed for timer counting during register
reads. When timer counting and register read processing are performed simultaneously, the
register value before TCNT counting down (with synchronization processing) is read.
Rev. 1.00, 02/04, page 380 of 804
Channel
0
1
2
Interrupt Sources and Priorities
Usage Notes
Interrupt Source
TUNI0
TUNI1
TUNI2
Underflow interrupt 0
Description
Underflow interrupt 1
Underflow interrupt 2
Priority
High
Low