HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 160

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

set if the guard-bit parts are used for large number representation. Some DC bit generation
examples in overflow mode are shown in figure 3.13.
Signed Greater Than Mode: CS[2:0] = B'100: The DC bit indicates whether or not the source 1
data (signed) is greater than the source 2 data (signed) as the result of compare operation PCMP.
Therefore, the PCMP operation should be executed before the conditional operation is executed
under this condition mode. This mode is similar to the Negative Value Mode described before,
because the result of a compare operation is a positive value if the source 1 data is greater than the
source 2 data. However, the signed bit of the result shows a negative value if the compare
operation yields a result beyond the range of the destination operand, including the guard-bit parts
(called “Over-range”), even though the source 1 data is greater than the source 2 data. The DC bit
is updated concerning this type of special case in this condition mode. The equation below shows
the definition of getting this condition:
When the PCMP operation is executed under this condition mode, the result of the DC bit is the
same as the T bit’s result of the CMP/GT operation of the CPU instruction.
Signed Greater Than or Equal Mode: CS[2:0] = B'101: The DC bit indicates whether the
source 1 data (signed) is greater than or equal to the source 2 data (signed) as the result of compare
operation PCMP. Therefore, the PCMP operation should be executed before the conditional
operation is executed under this condition mode. This mode is similar to the Signed Greater Than
Mode described before but the equal case is also included in this mode. The equation below shows
the definition of getting this condition:
When the PCMP operation is executed under this condition mode, the result of the DC bit is the
same as the T bit’s result of a CMP/GE operation of the CPU instruction.
The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]
bits. See the negative value mode part above. The Z bit always indicates the same state as the DC
bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit
Rev. 1.00, 02/04, page 122 of 804
DC = ~ {(Negative ^ Over-range) | Zero}
DC = ~ (Negative ^ Over-range)
+)
Figure 3.13 DC Bit Generation Examples in Overflow Mode
Guard bits
1111
1111
111111110111111111111111
1111
1111
Overflow case
Example 1
1111
1000
Overflow detecting field
1111
0000
1111
0000
1111
0000
+)
1111
1111
111111111000000000000000
Guard bits
1111
1111
Non overflow case
Example 2
1111
1000
Overflow detecting field
1111
0000
1111
0000
1111
0001