HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 20

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

23.5 Port G................................................................................................................................ 635
23.6 Port H................................................................................................................................ 637
Section 24 Pin Function Controller (PFC) ........................................................ 639
24.1 Overview........................................................................................................................... 639
24.2 Register Descriptions........................................................................................................ 641
Section 25 User Break Controller...................................................................... 655
25.1 Features............................................................................................................................. 655
25.2 Register Descriptions........................................................................................................ 657
25.3 Operation .......................................................................................................................... 671
Rev. 1.00, 02/04, page xx of xxxviii
23.4.2 Port E Data Register (PEDR)............................................................................... 633
23.5.1 Register Description ............................................................................................ 635
23.5.2 Port G Data Register (PGDR).............................................................................. 636
23.6.1 Register Description ............................................................................................ 637
23.6.2 Port H Data Register (PHDR).............................................................................. 637
24.2.1 Port A Control Register (PACR) ......................................................................... 641
24.2.2 Port B Control Register (PBCR).......................................................................... 643
24.2.3 Port D Control Register (PDCR) ......................................................................... 644
24.2.4 Port E Control Register (PECR) .......................................................................... 646
24.2.5 Port G Control Register (PGCR) ......................................................................... 647
24.2.6 Port H Control Register (PHCR) ......................................................................... 649
24.2.7 Pin Select Register A (PSELA) ........................................................................... 650
24.2.8 I/O Buffer Hi-Z Control Register A (HIZCRA) .................................................. 652
24.2.9 Noise Canceller Control Register (NCCR).......................................................... 654
25.2.1 Break Address Register A (BARA).................................................................... 657
25.2.2 Break Address Mask Register A (BAMRA)........................................................ 658
25.2.3 Break Bus Cycle Register A (BBRA).................................................................. 658
25.2.4 Break Address Register B (BARB) ..................................................................... 660
25.2.5 Break Address Mask Register B (BAMRB) ........................................................ 661
25.2.6 Break Data Register B (BDRB)........................................................................... 661
25.2.7 Break Data Mask Register B (BDMRB).............................................................. 662
25.2.8 Break Bus Cycle Register B (BBRB) .................................................................. 663
25.2.9 Break Control Register (BRCR) .......................................................................... 664
25.2.10 Execution Times Break Register (BETR)............................................................ 667
25.2.11 Branch Source Register (BRSR).......................................................................... 669
25.2.12 Branch Destination Register (BRDR).................................................................. 670
25.3.1 Flow of the User Break Operation ....................................................................... 671
25.3.2 Break on Instruction Fetch Cycle ........................................................................ 672
25.3.3 Break on Data Access Cycle................................................................................ 673
25.3.4 Break on X/Y-Memory Bus Cycle ...................................................................... 674
25.3.5 Sequential Break.................................................................................................. 674
25.3.6 Value of Saved Program Counter ........................................................................ 675