HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 35

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 8 Interrupt Controller (INTC)
Table 8.1
Table 8.2
Table 8.3
Table 8.4
Section 9 Bus State Controller (BSC)
Table 9.1
Table 9.2
Table 9.3
Table 9.4
Table 9.5
Table 9.6
Table 9.7
Table 9.7
Table 9.8
Table 9.8
Table 9.9
Table 9.9
Table 9.10
Table 9.11
Table 9.12
Section 10 Direct Memory Access Controller (DMAC)
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 10.5
Table 10.6
Table 10.7
Table 10.8
Section 11 Clock Pulse Generator (CPG)
Table 11.1
Table 11.2
Pin Configuration.................................................................................................. 201
Interrupt Sources and IPRA to IPRH.................................................................... 203
Correspondence between Interrupt Sources and IMR0 to IMR9/IMCR0
Interrupt Exception Handling Sources and Priority .............................................. 213
Pin Configuration.................................................................................................. 220
Address Space Map of External Address Space ................................................... 223
16-Bit External Device/Big Endian Access and Data Alignment ......................... 248
8-Bit External Device/Big Endian Access and Data Alignment........................... 249
16-Bit External Device/Little Endian Access and Data Alignment ...................... 249
8-Bit External Device/Little Endian Access and Data Alignment ........................ 250
Relationship between CS3BCR.BSZ[1:0], SDCR.A3ROW[1:0],
Relationship between CS3BCR.BSZ[1:0], SDCR.A3ROW[1:0],
Relationship between CS3BCR.BSZ[1:0], SDCR.A3ROW[1:0],
Relationship between CS3BCR.BSZ[1:0], SDCR.A3ROW[1:0],
Relationship between CS3BCR.BSZ[1:0], SDCR.A3ROW[1:0],
Relationship between CS3BCR.BSZ[1:0], SDCR.A3ROW[1:0],
Relationship between Access Size and Number of Bursts.................................... 267
Access Address in SDRAM Mode Register Write ............................................... 283
Relationship between Data Bus Width, Access Size, and Number of Bursts ....... 285
Pin Configuration.................................................................................................. 299
DMARS Settings .................................................................................................. 312
Selecting External Request Modes with the RS Bits ............................................ 315
Selecting External Request Detection with DL, DS Bits ...................................... 316
Selecting External Request Detection with DO Bit .............................................. 316
Selecting On-Chip Peripheral Module Request Modes with the RS3
Supported DMA Transfers.................................................................................... 321
Relationship of Request Modes and Bus Modes by DMA Transfer Category ..... 327
Clock Pulse Generator Pins Configuration ........................................................... 336
Clock Operating Modes ........................................................................................ 337
to IMCR9.............................................................................................................. 209
SDCR.A3COL[1:0], and Address Multiplex Output (1)-1................................... 261
SDCR.A3COL[1:0], and Address Multiplex Output (1)-2................................... 262
SDCR.A3COL[1:0], and Address Multiplex Output (2)-1................................... 263
SDCR.A3COL[1:0], and Address Multiplex Output (2)-2................................... 264
SDCR.A3COL[1:0], and Address Multiplex Output (3)-1................................... 265
SDCR.A3COL[1:0], and Address Multiplex Output (3)-2................................... 266
to RS0 Bits............................................................................................................ 317
Rev. 1.00, 02/04, page xxxv of xxxviii