HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 71

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Uxy Area: The Uxy area that can be used when the DSP bit in SR is set to 1 in user mode is
mapped to the on-chip memory of this LSI. Accessing this area when the DSP bit is 0 in user
mode will result in an address error. This area cannot be accessed through the cache. For details on
the Uxy area, see section 6, X/Y Memory and section 7, U Memory. For details on the DSP bit,
see section 3, DSP Operating Unit.
Note: * Whether the cache is used or not is determined according to the CE bit in the cache
2.2.2
The physical address space obtained by address translation of addresses output from the CPU is
referred to as the physical address space. From the hardware view, the addresses of the physical
address space are used on the I bus. Similar to the logical address space, this LSI supports a 32-bit
physical address space. However, as shown in figure 2.4, the upper three bits of the 32 bits are
masked and handled as a shadow. Therefore, only 29 bits are actually used to access the physical
address space and 0.5 Gbytes of physical memory can be accessed. Replacing the upper three bits
of an address in this area with 0s makes the address in the corresponding physical address space.*
For details on the physical address space, see section 9, Bus State Controller (BSC).
Bus masters other than the CPU, e.g. DMAC, are directly connected to the I bus. Therefore,
instead of handling the logical address space, they directly handle the physical address space.
Note: * Since the on-chip I/O registers can be accessed only if the upper three bits of a logical
Physical Address Space
address are set to 111 (corresponding to the P4 area in privileged mode), the upper three
bits are output with the same values of 111 on the I bus.
control register (CCR1).
H'E0000000
H'F0000000
H'F1000000
H'F2000000
H'FC000000
H'FFFFFFFF
Figure 2.3 P4 Area
Cache data array area
Control register area
Cache address area
Reserved area
Reserved area
(256 Mbytes)
(160 Mbytes)
(16 Mbytes)
(16 Mbytes)
(64 Mbytes)
Rev. 1.00, 02/04, page 33 of 804