HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 203

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

4.3.2
CPU address error:
• Conditions
• Types
• Save address
• Exception code
• Remarks
Illegal general instruction exception:
• Conditions
Note: For details on undefined code, refer to section 2.6.2, Operation Code Map. When an
• Types
• Save address
 Instruction is fetched from odd address (4n + 1, 4n + 3)
 Word data is accessed from addresses other than word boundaries (4n + 1, 4n + 3)
 Longword is accessed from addresses other than longword boundaries (4n + 1, 4n + 2,
 The area ranging from H'80000000 to H'FFFFFFFF in logical space is accessed in user
Instruction synchronous, re-execution type
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
An exception occurred during read: H'0E0
An exception occurred during write: H'100
The virtual address (32 bits) that caused the exception is set in TEA.
 When undefined code not in a delay slot is decoded
 When a privileged instruction not in a delay slot is decoded in user mode
Instruction synchronous, re-execution type
An instruction address where an exception occurs
4n + 3)
mode
Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR
with LDC/STC are not privileged instructions.
undefined code other than H'FC00 to H'FFFF is decoded, operation cannot be guaranteed.
General Exceptions
Rev. 1.00, 02/04, page 165 of 804