HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 526

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Receive Data Sampling Timing and Receive Margin: As an example, when the sampling rate is
1/16, the SCIF operates on a base clock with a frequency of 8 times the transfer rate.
In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the
base clock. Receive data is latched at the rising edge of the eighth base clock pulse.
Figure 16.17 shows an example of asynchronous mode receive data sampling timing in
asynchronous mode.
Base clock
Receive data
(RxD)
Synchronized
sampling
timing
Data
sampling
timing
The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
When D = 0.5 and F = 0:
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Rev. 1.00, 02/04, page 488 of 804
M: Receive margin (%)
N:
D:
L:
F:
Ratio of clock frequency to bit rate (N = 16)
Clock duty cycle (D = 0 to 1.0)
Frame length (L = 9 to 12)
Absolute deviation of clock frequency
M = (0.5 – 1/(2 × 16)) × 100% = 46.875% ............................................. (2)
M = 0.5 –
0
Figure 16.17 Receive Data Sampling Timing in Asynchronous Mode
1
Start bit
2
8 clocks
3
2N
4
1
5
16 clocks
– (L – 0.5)F –
6
7
8
9 10 11 12 13 14 15
- 7.5 clocks
D – 0.5
N
0
(1 + F)
1
+ 7.5 clocks
2
3
4
100% ...........................
D0
5
6
7
8
9
10 11 12 13 14 15
(1)
0
1
2
D1
3
4
5