HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 716

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

(Example 1-4)
• Register specifications
(Example 1-5)
• Register specifications
Rev. 1.00, 02/04, page 678 of 804
BARA = H'00037226, BAMRA = H'00000000, BBRA = H'005A, BARB = H'0003722E,
BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00000008
Specified conditions: Channel A/channel B sequential mode
 Channel A
 Channel B
BARA = H'00000500, BAMRA = H'00000000, BBRA = H'0057, BARB = H'00001000,
BAMRB = H'00000000, BBRB = H'0057, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00300001, BETR = H'0005
Specified conditions: Channel A/channel B independent mode
 Channel A
 Channel B
Address: H'00037226, Address mask: H'00000000
Bus cycle: L bus/instruction fetch (before instruction execution)/write/word
Address: H'0003722E, Address mask: H'00000000
Data:
Bus cycle: L bus/instruction fetch (before instruction execution)/read/word
Since instruction fetch is not a write cycle on channel A, a sequential condition does not
match. Therefore, no user break occurs.
Address: H'00000500, Address mask: H'00000000
Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword
Address: H'00001000, Address mask: H'00000000
Data:
Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword
The number of execution-times break enable (5 times)
On channel A, a user break occurs before an instruction of address H'00000500 is
executed. On channel B, a user break occurs after the instruction of address H'00001000
are executed four times and before the fifth time.
H'00000000, Data mask: H'00000000
H'00000000, Data mask: H'00000000