HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 456

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 15.10 Conditions to Issue Receive Request
The number of stages of the FIFO is always sixteen even if the data area or empty area exceeds the
FIFO size (the number of FIFOs). Accordingly, an overflow error or underflow error occurs if data
area or empty area exceeds sixteen FIFO stages. The FIFO transmit or receive request is canceled
when the above condition is not satisfied even if the FIFO is not empty or full.
Number of FIFOs: The number of FIFO stages used in transmission and reception is indicated by
the following register.
• Transmit FIFO: The number of empty FIFO stages is indicated by the TFUA4 to TFUA0 bits
• Receive FIFO: The number of valid data stages is indicated by the RFUA4 to RFUA0 bits in
Rev. 1.00, 02/04, page 418 of 804
RFWM2 to RFWM0
000
100
101
110
111
in SIFCTR.
SIFCTR.
The above indicate possible data numbers that can be transferred by the CPU or DMAC.
Number of
Requested Stages
1
4
8
12
16
Receive Request
Valid data is 1 stage or more
Valid data is 4 stages or more
Valid data is 8 stages or more
Valid data is 12 stages or more
Valid data is 16 stages
Used Areas
Smallest
Largest