HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 280

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

9.4.4
SDCR is a 32-bit register that specifies the method to refresh and access SDRAM, and the types of
SDRAMs to be connected.
SDCR is initialized by a power-on reset, but not by a manual reset or in standby mode and holds
the previous value. Bits other than RFSH and RMODE should be written to at the initialization
settings and not be changed afterward. When writing to RFSH and RMODE, the values before
writing should be written to the other bits. The area 3 should not be accessed until this register
setting has been completed while the synchronous DRAM is used.
Rev. 1.00, 02/04, page 242 of 804
Bit
31 to 13
12
11
SDRAM Control Register (SDCR)
Bit Name

SLOW
RFSH
Initial
Value
All 0
0
0
R/W Description
R
R/W Low-Frequency Mode
R/W Refresh Control
Reserved
These bits are always read as 0. The write value should
always be 0. If 1 is written to this bit, correct operation cannot
be guaranteed.
Specifies the output timing of command, address, and write
data for SDRAM and the latch timing of read data from
SDRAM. Setting this bit makes the hold time for command,
address, write and read data. This mode is suitable for
SDRAM with low-frequency clock.
0: Command, address, and write data for SDRAM is output
1: Command, address, and write data for SDRAM is output
at the falling edge of CKIO. Read data from SDRAM is
latched at the falling edge of CKIO.
Specifies whether or not the refresh operation of the SDRAM
is performed.
0: No refresh
1: Refresh
at the rising edge of CKIO. Read data from SDRAM is
latched at the rising edge of CKIO.