HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 338

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HD6417660

Manufacturer Part Number
HD6417660
Description
Renesas 32-Bit RISC Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
10.3
Register Descriptions
Register configuration of DMAC is described below. See section 27, List of Registers, for the
addresses of these registers and the state of them in each processing status. In the following
description of registers for each channel, for example, SAR for channel 0 is described as SAR_0.
Channel 0:
• DMA source address register_0 (SAR_0)
• DMA destination address register_0 (DAR_0)
• DMA transfer count register_0 (DMATCR_0)
• DMA channel control register_0 (CHCR_0)
• DMA initial address register_0 (IAR_0)
Channel 1:
• DMA source address register_1 (SAR_1)
• DMA destination address register_1 (DAR_1)
• DMA transfer count register_1 (DMATCR_1)
• DMA channel control register _1 (CHCR_1)
• DMA initial address register_1 (IAR_1)
Channel 2:
• DMA source address register_2 (SAR_2)
• DMA destination address register_2 (DAR_2)
• DMA transfer count register_2 (DMATCR_2)
• DMA channel control register_2 (CHCR_2)
• DMA initial address register_2 (IAR_2)
Channel 3:
• DMA source address register_3 (SAR_3)
• DMA destination address register_3 (DAR_3)
• DMA transfer count register_3 (DMATCR_3)
• DMA channel control register_3 (CHCR_3)
• DMA initial address register_3 (IAR_3)
Rev. 1.00, 02/04, page 300 of 804

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