HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 70

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

P0/U0 Area: This area is called the P0 area when the CPU is in privileged mode and the U0 area
when in user mode. For the P0 and U0 areas, access using the cache is enabled.*
P1 Area: The P1 area is defined as a privileged area that is cacheable.* Normally, this area
contains programs that operate at high-speed in privileged mode, such as the kernel of the
operating system (OS) and the exception handler.
P2 Area: The P2 area is defined as a privileged area that is not cacheable. The reset processing
program that is initiated when a transition is made to the reset state is written from the start
address of the P2 area (H'A0000000). Normally, this area contains programs that are needed to
initiate the OS, such as the system initial setting routine. Note that access to several on-chip I/O
registers requires the program to be saved in the P2 area.
P3 Area: The P3 area is defined as a privileged area that is cacheable.*
P4 Area: The P4 area is a control space that is not cacheable and can be accessed only in
privileged mode. Figure 2.3 shows the P4 area in detail. Several on-chip I/O registers are assigned
to this area. For details on I/O registers which are assigned to this area, see section 27, List of
Registers.
Rev. 1.00, 02/04, page 32 of 804
H'00000000
H'80000000
H'A0000000
H'C0000000
H'E0000000
H'FFFFFFFF
Note: * Exists only when the DSP bit in SR is 1.
P1 area (512 Mbytes)
P2 area (512 Mbytes)
P3 area (512 Mbytes)
P4 area (512 Mbytes)
P0 area (2 Gbytes)
In privileged mode
Not cacheable
Not cacheable
Figure 2.2 Logical Address Space
Cacheable
Cacheable
Cacheable
U0 area (2 Gbytes)
Not cacheable
Address error
Address error
In user mode
Cacheable
Uxy area*
H'A5000000
H'A5FFFFFF