HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 377

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Notes: 1. Initial value immediately after reset in each mode.
Cautions:
Mode
7
FRQCR
Register
Value
H'1105
H'1106
H'1111
H'1202
H'1204
H'1206
H'1303
H'1305
H'1306
H'1313
H'1333
2. The value is settable when the boot function is used.
1. Input of divider circuit 1 becomes PLL circuit 1 output
2. Input of PLL circuit 1 becomes:
3. The frequency of the internal clock becomes:
4. The frequency of the peripheral clock becomes:
5. ×1, ×2, ×3, or ×4 can be used as the multiplication ratio of PLL circuit 1. ×1, ×1/2, ×1/3,
6. The output frequency of PLL circuit 1 is the product of the CKIO frequency and the
7. Bus clock frequency is always set to be equal to the frequency of the CKIO pin.
8. Clock ratios in table 11.3 are ratios of each frequency to one input clock frequency.
The boot function should not be used with values other than these values.
There is a limitation in the SCIF transfer rate which can be set according to the input
clock frequency. Refer to section 17.5.2, Clock Frequency and Data Transfer Rate
when Using Boot Function in section 17, Boot Function (BOOT) for detail.
CKIO pin input in mode 7
PLL circuit2 output in modes 5 and 6
The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL
circuit 1, and the division ratio of divider 1
Set the internal clock frequency not more 120 MHz (T.B.D). Do not set the internal clock
frequency lower than the frequency of the CKIO pin.
The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL
circuit 1, and the division ratio of divider 1. Set the peripheral clock frequency lower
than or equal to 30 MHz. Note that the frequency should not be higher than the CKIO
pin frequency.
×1/4, ×1/6, ×1/8 and ×1/12 can be selected as the division ratios of divider 1. Set the
rate using frequency control register (FRQCR).
multiplication ratio of PLL circuit 1. Use the output frequency not more than 120 MHz
(T.B.D).
PLL
Circuit 1
ON (×2)
ON (×2)
ON (×2)
ON (×3)
ON (×3)
ON (×3)
ON (×4)
ON (×4)
ON (×4)
ON (×4)
ON (×4)
PLL
Circuit 2
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Clock Ratio
(Iφ:Bφ:Pφ)
2:1:1/4
2:1:1/6
1:1:1
3:1:1
3:1:1/2
3:1:1/4
4:1:1
4:1:1/2
4:1:1/3
2:1:1
1:1:1
Input Clock
Frequency Range
20MHz to 60MHz
20MHz to 60MHz
20MHz to 30MHz
26.7MHz to 30MHz
26.7MHz to 40MHz
26.7MHz to 40MHz
20MHz to 30MHz
20MHz to 30MHz
20MHz to 30MHz
20MHz to 30MHz
20MHz to 30MHz
Rev. 1.00, 02/04, page 339 of 804
CKIO Pin
Frequency Range
20MHz to 60MHz
20MHz to 60MHz
20MHz to 30MHz
26.7MHz to 30MHz
26.7MHz to 40MHz
26.7MHz to 40MHz
20MHz to 30MHz
20MHz to 30MHz
20MHz to 30MHz
20MHz to 30MHz
20MHz to 30MHz