HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 195

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

4.1.2
EXPEVT is assigned to address H'FFFFFFD4 and consists of a 12-bit exception code. Exception
codes to be specified in EXPEVT are those for resets and general exceptions. These exception
codes are automatically specified by the hardware when an exception occurs. Only bits 11 to 0 of
EXPEVT can be re-written using the software.
Note: Initialized to H'000 at power-on reset and H'020 at manual reset.
4.1.3
INTEVT2 is assigned to address H'A4000000 and consists of a 12-bit exception code. Exception
codes to be specified in INTEVT2 are those for interrupt requests. These exception codes are
automatically specified by the hardware when an exception occurs. INTEVT2 cannot be modified
using the software.
4.1.4
TEA is assigned to address H'FFFFFFFC and stores the virtual address for an exception
occurrence when an exception related to memory accesses occurs. TEA can be modified using the
software.
Bit
31 to 12 
11 to 0
Bit
31 to 12 
11 to 0
Bit
31 to 0
Exception Event Register (EXPEVT)
Interrupt Event Register 2 (INTEVT2)
Exception Address Register (TEA)
Bit Name
EXPEVT
Bit Name
INTEVT2
Bit Name
TEA
All 0
*
All 0

All 0
Initial Value
Initial Value
Initial Value
R
R/W
R
R
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0. If 1 is written to these bits,
correct operation cannot be guaranteed.
12-bit Exception Code
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
12-bit Exception Code
Description
Virtual Address For Exception
Rev. 1.00, 02/04, page 157 of 804