HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 296

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

9.5.4
The number of cycles from CSn assertion to RD, WEn assertion can be specified by setting bits
SW1 and SW0 in CSnWCR. The number of cycles from RD, WEn negation to CSn negation can
be specified by setting bits HW1 and HW0. Therefore, a flexible interface to an external device
can be obtained. Figure 9.10 shows an example. A Th cycle and a Tf cycle are added before and
after an ordinary cycle, respectively. In these cycles, RD and WEn are not asserted, while other
signals are asserted. The data output is prolonged to the Tf cycle, and this prolongation is useful
for devices with slow writing operations.
Rev. 1.00, 02/04, page 258 of 804
CSn Assert Period Expansion
Write
Read
A23 to A0
DACKn*
D15 to D0
D15 to D0
Figure 9.10 CSn Assert Period Expansion
RD/WR
CKIO
WEn
CSn
Note: * The waveform for DACK is when active low is specified.
RD
BS
Th
T1
T2
Tf