HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 126

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Restrictions on Repeat Loop Control
1. Repeat control instruction assignment
2. Illegal instruction one or more instructions following the repeat detection instruction
Note: This restriction applies to all instructions for a repeat loop consisting of one to three
3. Instructions prohibited during repeat loop (In a repeat loop consisting of four or more
Note: Multiple repeat loops cannot be guaranteed. Describe the inner loop by repeat control
4. Branching to an instruction following the repeat detection instruction and restriction on an
Rev. 1.00, 02/04, page 88 of 804
The SETRC instruction must be executed after executing the LDRS and LDRE instructions.
In addition, note that at least one instruction is required between the SETRC instruction and a
repeat start instruction.
If one of the following instructions is executed between an instruction following a repeat
detection instruction to a repeat end instruction, an illegal instruction exception occurs.
 Branch instructions
 Repeat control instructions
 Load instructions for SR, RS, and RE registers
instructions)
The following instructions must not be placed between the repeat start instruction and repeat
detection instruction in a repeat loop consisting of four or more instructions. Otherwise, the
correct operation cannot be guaranteed.
 Repeat control instructions
 Load instructions for SR, RS, and RE registers
CPU can recognize the repeat loop. Therefore, when the execution branches to an instruction
following the repeat detection instruction, the control will not be passed to a repeat start
instruction after executing a repeat end instruction because the repeat loop is not recognized by
the CPU. In this case, the RC[11:0] bits of the SR register will not be changed.
 If a conditional branch instruction is used in the repeat loop, an instruction before a repeat
exception acceptance
Execution of a repeat detection instruction must be completed without any branch so that the
BRA, BSR, BT, BF, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR, JMP, TRAPA
SETRC, LDRS, LDRE
LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+,RS
SETRC, LDRS, LDRE
LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+,RS
detection instruction must be specified as a branch destination.
instructions and to three instructions including a repeat end instruction.
instructions, and the external loop by other instructions such as DT or BF/S.