HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 196

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

4.2
4.2.1
In exception handling, the contents of the program counter (PC) and status register (SR) are saved
in the saved program counter (SPC) and saved status register (SSR), respectively, and execution of
the exception handler is invoked from a vector address. The return from exception handler (RTE)
instruction is issued by the exception handler routine on completion of the routine, restoring the
contents of PC and SR to return to the processor state at the point of interruption and the address
where the exception occurred.
A basic exception handling sequence consists of the following operations. If an exception occurs
and the CPU accepts it, operations 1 to 8 are executed.
1. The contents of PC are saved in SPC.
2. The contents of SR are saved in SSR.
3. The block (BL) bit in SR is set to 1, masking any subsequent exceptions.
4. The mode (MD) bit in SR is set to 1 to place the privileged mode.
5. The register bank (RB) bit in SR is set to 1.
6. When an exception source is a general exception, an exception code identifying the exception
7. If a TRAPA instruction is executed, an 8-bit immediate data specified by the TRAPA
8. Instruction execution jumps to the designed exception vector address to invoke the handler
The above operations from 1 to 8 are executed in sequence. During these operations, no other
exceptions may be accepted unless multiple exception acceptance is enabled.
In an exception handling routine for a general exception, the appropriate exception handling must
be executed based on an exception source determined by the EXPEVT. In an interrupt exception
handling routine, the appropriate exception handling must be executed based on an exception
source determined by the INTEVT2. After the exception handling routine has been completed,
program execution can be resumed by executing an RTE instruction. The RTE instruction causes
the following operations to be executed.
Rev. 1.00, 02/04, page 158 of 804
event is written to EXPEVT. When an exception source is an interrupt, an exception code is
written to INTEVT2.
instruction is set to TRA. For an exception related to memory accesses, the virtual address
where the exception occurred is written to TEA.
routine.
Exception Handling Function
Exception Handling Flow