HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 320

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HD6417660

Manufacturer Part Number
HD6417660
Description
Renesas 32-Bit RISC Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Power-Down Mode: If the PDOWN bit of the SDCR register is set to 1, the SDRAM is placed in
the power-down mode by bringing the CKE signal to the low level in the non-access cycle. This
power-down mode can effectively lower the power consumption in the non-access cycle.
However, please note that if an access occurs in power-down mode, a cycle of overhead occurs
because a cycle is inserted to assert the CKE signal in order to cancel the power-down mode.
After the SDRAM access ends, it is possible to shift to the power down mode again by accessing
the memory other than SDRAM (CKE becomes Low level).
Figure 9.26 shows the access timing in power-down mode.
Rev. 1.00, 02/04, page 282 of 804
D15 to D0
A23 to A0
DACK*
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
RD/WR
DQMn
A11*
CKIO
CKE
RAS
CAS
CS3
BS
1
2
2. The waveform for DACK is when active low is specified.
Power-down
Figure 9.26 Power-Down Mode Access Timing
Tnop
Tr
Tc1
Td1
Tde
Tap
Power-down

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