HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 366

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Bus Mode and Channel Priority Order: When a given channel 1 is transferring in burst mode
and there is a transfer request to a channel 0 with a higher priority in fixed mode (CH0 > CH1),
the transfer of channel 0 will begin immediately.
At this time, the channel 1 transfer will continue when the channel 0 transfer has completely
finished, even if channel 0 is operating in burst mode.
When channel 0 is operating in cycle steal mode, 1 will begin operating again without releasing
bus mastership after channel 0 with a higher priority completes the transfer of one transfer unit.
Then transfer is carried out between the two channels in the order channel 0, channel 1, channel 0,
channel 1. In other words, the CPU cycle after transfer in cycle steal mode is switched with
transfer in burst mode (hereafter, this is called preferential execution of burst mode). This example
is shown in figure 10.12. When more than two channels in burst mode are conflicted, transfer on a
channel with highest priority among those channels is executed.
When transfers of more than two channels are performed, the bus is not given to the bus master
until conflicted transfers in burst mode have been completed.
The priority order in round-robin mode is changed as is shown in figure 10.3. Note that in the
burst mode, channel for cycle steal and channel for burst mode should not be mixed.
10.4.6
Number of Bus Cycle States: When the DMAC is the bus master, the number of bus cycle states
is controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master.
For details, see section 9, Bus State Controller (BSC).
DREQ Pin Sampling Timing: Figures 10.13 to 10.16 show the DREQ input sampling timings in
each bus mode.
Rev. 1.00, 02/04, page 328 of 804
Number of Bus Cycle States and DREQ Pin Sampling Timing
Priority: CH0 > CH1
CH0: Cycle-steal mode
CH1: Burst mode
Figure 10.12 Bus State when Multiple Channels Are Operating
CPU
CPU
DMA
CH1
DMAC CH1
Burst mode
DMA
CH1
DMA
CH0
CH0
DMAC CH0 and CH1
Cycle steal mode
DMA
CH1
CH1
DMA
CH0
CH0
DMA
CH1
DMAC CH1
Burst mode
DMA
CH1
CPU
CPU