HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 714

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

25.3.7
1. Setting PCTE in BRCR to 1 enables PC traces. When branch (branch instruction, and interrupt
2. The values stored in BRSR and BRDR are as given below due to the kind of branch.
3. BRSR and BRDR have eight pairs of queue structures. The top of queues is read first when the
25.3.8
Break Condition Specified for L Bus Instruction Fetch Cycle:
(Example 1-1)
• Register specifications
Rev. 1.00, 02/04, page 676 of 804
exception) is generated, the branch source address and branch destination address are stored in
BRSR and BRDR, respectively.
 If a branch occurs due to a branch instruction, the address of the branch instruction is saved
 If a branch occurs due to an interrupt or exception, the value saved in SPC due to exception
When a repeat loop of the DSP extended function is used, control being transferred from the
repeat end instruction to the repeat start instruction is not recognized as a branch, and the
values are not stored in BRSR and BRDR.
address stored in the PC trace register is read. BRSR and BRDR share the read pointer. Read
BRSR and BRDR in order, the queue only shifts after BRDR is read. After switching the
PCTE bit (in BRCR) off and on, the values in the queues are invalid.
BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BARB = H'00008010,
BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00300400
Specified conditions: Channel A/channel B independent mode
 Channel A
 Channel B
in BRSR and the address of the branch destination instruction is saved in BRDR.
occurrence is saved in BRSR and the start address of the exception handling routine is
saved in BRDR.
Address: H'00000404, Address mask: H'00000000
Bus cycle:
Address:
Data:
Bus cycle:
PC Trace
Usage Examples
L bus/instruction fetch (after instruction execution)/read (operand size is not
included in the condition)
H'00008010, Address mask: H'00000006
H'00000000, Data mask: H'00000000
L bus/instruction fetch (before instruction execution)/read (operand size is
not included in the condition)