HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 523

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

16.5
SCIF Interrupt Sources and DMAC
The SCIF supports six interrupts in asynchronous mode—transmit-FIFO-data-empty (TXI),
transmit-data-stop (TDI), receive-error (ERI), receive-FIFO-data-full (RXI), break-receive (BRI),
and receive-data-ready (DRI). In clock synchronous mode, the SCIF supports two interrupts—
transmit-FIFO-data-empty (TXI) and receive-FIFO-data-full (RXI). The vectors of each interrupt
are the same.
Table 16.4 shows the interrupt sources. The interrupt sources can be enabled or disabled by means
of the TIE, RIE, ERIE, BRIE, DRIE, and TSIE bits in SCSCR.
When the TDFE flag in SCSSR is set to 1, a TXI interrupt request is generated. When the TSF
flag in SCSSR is set to 1, a TDI interrupt request is generated. The DMAC can be activated and
data transfer performed on generation of TXI and TDI interrupt requests. The DMAC requests of
TXI and TDI are assigned to the same vector.
When the RDF flag in SCSSR is set to 1, an RXI interrupt request is generated. The DMAC can
be activated and data transfer performed on generation of an RXI interrupt request.
When using the DMAC for transmission/reception, set and enable the DMAC before making SCIF
settings. See section 10, Direct Memory Access Controller (DMAC), for details of the DMAC
setting procedure.
When the ER flag in SCSSR is set to 1, an ERI interrupt request is generated.
When the BRK flag in SCSSR is set to 1, a BRI interrupt request is generated.
When the DR flag in SCSSR is set to 1, a DRI interrupt request is generated.
When the TSF flag in SCSSR is set to 1, a TDI interrupt request is generated.
The vectors of TXI, TDI, ERI, BRI, RXI and DRI are the same.
The DMAC activation and interrupts cannot be generated simultaneously by the same source. The
following procedure should be used for the DMAC activation.
1. Set the interrupt enable bits (TIE, RIE and TDIE) corresponding to the generated source to 1.
2. Mask the corresponding interrupt requests by using the interrupt mask register of the interrupt
controller.
Rev. 1.00, 02/04, page 485 of 804