HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 227

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

5.4.3
Invalidating Specific Entries: Specific cache entries can be invalidated by writing 0 to the
entry’s V bit in the memory-mapped cache access. When the A bit is 1, the tag address specified
by the write data is compared to the tag address within the cache selected by the entry address, and
a match is found, the entry is written back if the entry’s U bit is 1 and the V bit and U bit specified
by the write data are written. If no match is found, there is no operation. In the example shown
below, R0 specifies the write data and R1 specifies the address.
Reading the Data of a Specific Entry: To read the data field of a specific entry is enabled by the
memory-mapped cache access. The longword indicated in the data field of the data array in figure
5.4 is read into the register. In the example shown below, R0 specifies the address and R1 shows
what is read.
; R0=H′01100010; specification of data for address array access, tag
address=B′0 0001 0001 0000 0000 00, LRU = B′00 0001, U=0, V=0
; R1=H′F0000088; specification of address to be accessed in address
array access, way = B′00, entry address=B′00001000, A=1
;
MOV.L R0,@R1
; R0=H′F100 004C; specification of address for data array access,
way=B′00, entry address=B′00000100, L=B′11
;
MOV.L @R0,R1 ; Longword 3 is read.
Usage Examples
Rev. 1.00, 02/04, page 189 of 804