HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 693

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

The user break controller (UBC) provides functions that simplify program debugging. These
functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug
programs without using an in-circuit emulator. Break conditions that can be set in the UBC are
instruction fetch or data read/write access, data size, data contents, address value, and stop timing
in the case of instruction fetch.
25.1
The UBC has the following features:
1. The following break comparison conditions can be set.
2. A user-designed user-break condition exception processing routine can be run.
3. In an instruction fetch cycle, it can be selected that a break is set before or after an instruction
4. Maximum repeat times for the break condition (only for channel B): 2
5. Eight pairs of branch source/destination buffers.
Number of break channels: two channels (channels A and B)
User break can be requested as either the independent or sequential condition on channels A
and B (sequential break setting: channel A and then channel B match with break conditions,
but not in the same bus cycle).
 Address
 Data
 Bus cycle
 Read/write
 Operand size
is executed.
Comparison bits are maskable in 1-bit units; user can mask addresses at lower 12 bits (4-k
page), lower 10 bits (1-k page), or any size of page, etc.
One of the four address buses (L-bus address (LAB), I-bus address(IAB), X-memory
address bus (XAB), and Y-memory address bus (YAB)) can be selected.
Only on channel B, 32-bit maskable.
One of the four data buses (L-bus data (LDB), I-bus data (IDB), X-memory data bus
(XDB) and Y-memory data bus (YDB)) can be selected.
Instruction fetch or data access
Byte, word, and longword
Features
Section 25 User Break Controller
Rev. 1.00, 02/04, page 655 of 804
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