upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 95
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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Pin Functions
Table 2-54
Table 2-55
DFEN0 register contents
Assignment of input signals to bit positions for register DFEN0
Preliminary User’s Manual U17566EE1V2UM00
a)
Bit
position
Bit position
15 to 0
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
Note that for high clock rates of the Clocked Serial Interface, the digital filter should
be disabled. Otherwise, desired input pulses may be removed by the digital filter.
Bit name
DFENC0
DFENC1
DFENC2
DFENC3
DFENC4
DFENC5
DFENC6
DFENC7
DFENC8
DFENC9
DFENC10 TIP20
DFENC11 TIP21
DFENC12 TIP30
DFENC13 TIP31
DFENC14 TIG01
DFENC15 TIG02
Bit name
DFENC[15:0]
Input signal
SIB0
SIB1
SIB2
SCKIB0
SCKIB1
SCKIB2
TIP00
TIP01
TIP10
TIP11
Enables/disables the digital noise elimination filter for
the corresponding input signal:
For an assignment of bit positions to input signals see
table Table 2-55.
0: Digital filter is disabled.
1: Digital filter is enabled.
Description
CSIB0 data input
CSIB1 data input
CSIB2 data input
CSIB0 clock input
CSIB1 clock input
CSIB2 clock input
Timer TMP0 channel 0 capture input
Timer TMP0 channel 1 capture input
Timer TMP1 channel 0 capture input
Timer TMP1 channel 1 capture input
Timer TMP2 channel 0 capture input
Timer TMP2 channel 1 capture input
Timer TMP3 channel 0 capture input
Timer TMP3 channel 1 capture input
Timer TMG0 channel 1 capture input
Timer TMG0 channel 2 capture input
Function
a
a
a
a
a
a
Chapter 2
95
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