upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 251

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Bus and Memory Control (BCU, MEMC)
Memory Controller
Table 7-1
BCU
• VSB: V850 system bus
• VDB: V850 data bus
• VFB: V850 fetch bus
The Bus Control Unit (BCU) controls the access to on-chip peripherals, to
external memory controller (MEMC), the VSB RAM and VSB Flash of the
µPD70F3426 device.
For access to external devices, the BCU generates the necessary control
signals (chip select signals) for the Memory Controller.
The 64 MB address range is divided into 2-MB, 4-MB and 8-MB memory
banks. Each of the memory banks can be assigned to an external device via
the chip area select control registers CSC0 and CSC1.
If an instruction uses such an address, a chip select signal is generated. The
device supports four chip select signals (CS0, CS1, CS3 and CS4). Each chip
select signal covers a certain address range, also called “chip select area”. For
details see “Memory banks and chip select signals” on page 252.
Additional byte enable signals BE0 to BE3 indicate valid data on any of the four
bytes of the 32-bit data bus D[31:0].
The Memory Controller generates the control signals for access to the external
devices. For example, it generates the read strobe (RD) and the write strobe
(WR). From the 26 bit address of the CPU, the lower 24 bits are passed to the
external device.
If two chip select signals are specified in the CSCn registers for a single
memory bank, the priority control selects one of the chip select signals. The
priority order is given in “CSCn - Chip area select control registers” on
page 265.
The external signals of the Memory Controller and their state during and after
reset are listed in the following table:
Memory Controller external connections and reset states
All pins are in input port mode after reset. Refer to “Pin Functions” on page 33.
Preliminary User’s Manual U17566EE1V2UM00
Signal name
A[23:0]
D[31:16]
D[15:0]
CS0
CS1
CS3
CS4
BE0
BE1
BE2
BE3
RD
WR
WAIT
BCLK
I/O
O
I/O
O
O
O
O
O
I
O
State
during reset
tbd
Hi-Z (3-state)
tbd
tbd
tbd
Hi-Z (3-state)
tbd
tbd
tbd
Hi-Z (3-state)
State
after reset
O
Port input
O
I
O
Port input
O
O
I
Port input
Function
Address bus
Data bus
Chip select signal
Byte enable signal
Read strobe
Write strobe
Data wait
Bus clock
Chapter 7
251