upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 252

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 7
252
Configuration
µPD70F3426
Table 7-2
ROMC
7.2.1 Memory banks and chip select signals
Note
To access external ROM with page access function (page ROM), the Page
ROM Controller (ROMC) is provided. It can handle page widths from 8 to 128
bytes.
For more details, see “Page ROM Controller” on page 279.
If the concerned pins are configured as external memory bus pins change
between input and output is performed automatically by memory controller’s
read and write operations.
The microcontroller device supports interfacing with various memory devices.
To make the bus and Memory Controller suitable for the connected device, the
endian format, wait functions and idle state insertions can be configured.
For a detailed description, see “Configuration of Memory Access” on
page 282.
The 64 MB address range is divided into memory banks. Each memory bank
is assigned to one or more chip select (CSn) signals. If a memory bank is
configured for external access, access to that memory bank generates the
corresponding chip select signal (see Figure 7-3 on page 254). The
combination of memory banks that activate the same chip select signal is
called chip select area.
Figure 7-2 shows the memory map of the µPD70F3426.
The 1 MB VSB Flash memory is mapped to the address range 0010 0000
001F FFFF
The 32 KB VSB RAM memory is mapped to the address range 0060 0000
0060 5FFF
For access to the VSB Flash and VSB RAM the concerned BCU registers have
to be set up as shown in Figure 7-2
For details about the control settings refer to the description of the registers.
BCU register settings for µPD70F3426 VSB Flash and VSB RAM access
Preliminary User’s Manual U17566EE1V2UM00
Control bit
CSC0.CS0[3:0]
CSC0.CS2[3:0]
BEC.BE00
BEC.BE20
H
H
within bank 3. CS2 is assigned to the VSB RAM memory.
within bank 0. CS0 is assigned to the VSB Flash memory.
Required setting
0001
1000
0
0
B
B
Bus and Memory Control (BCU, MEMC)
Comment
• bank 0 assigned to CS0 for VSB Flash
• default, don’t change
• bank 3 assigned to CS2 for VSB RAM
• no default, must be changed
• little endian for VSB Flash
• default, don’t change
• little endian for VSB RAM
• default, don’t change
H
H
to
to