upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 404
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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Chapter 11
404
INTTPnCC0 signal
INTTPnCC1 signal
TPnCCR0 register
TPnCCR1 register
TOPn0 pin output
TOPn1 pin output
Figure 11-26
INTTPnOV signal
16-bit counter
TPnOVF bit
TPnCE bit
FFFFH
0000H
When the TPnCE bit is set to 1, 16-bit timer/event counter P starts counting,
and the output signals of the TOPn0 and TOPn1 pins are inverted. When the
count value of the 16-bit counter later matches the set value of the TPnCCRm
register, a compare match interrupt request signal (INTTPnCCm) is generated,
and the output signal of the TOPnm pin is inverted.
The 16-bit counter continues counting in synchronization with the count clock.
When it counts up to FFFFH, it generates an overflow interrupt request signal
(INTTPnOV) at the next clock, is cleared to 0000H, and continues counting. At
this time, the overflow flag (TPnOPT0.TPnOVF bit) is also set to 1. Clear the
overflow flag to 0 by executing the CLR instruction by software.
The TPnCCRm register can be rewritten while the counter is operating. If it is
rewritten, the new value is reflected at that time, and compared with the count
value.
Basic timing in free-running timer mode (compare function)
Preliminary User’s Manual U17566EE1V2UM00
D
10
D
00
D
CLR instruction
Cleared to 0 by
10
D
00
D
10
D
00
Cleared to 0 by
CLR instruction
D
11
D
01
16-bit Timer/Event Counter P (TMP)
Cleared to 0 by
CLR instruction
D
11
D
D
D
01
01
11
CLR instruction
Cleared to 0 by
D
11
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