upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 580

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 18
580
Condition for clearing (SPIEn = 0)
• Cleared by instruction
• After reset
During address transfer, an interrupt occurs at the falling edge of the ninth clock regardless of this bit setting. This
bit setting becomes valid when the address transfer is completed. In master mode, a wait is inserted at the falling
edge of the ninth clock during address transfer. For a slave device that has received a local address, a wait is
inserted at the falling edge of the ninth clock after an ACK signal is issued. When the slave device has received
an extension code, however, a wait is inserted at the falling edge of the eighth clock.
Condition for clearing (WTIMn = 0)
• Cleared by instruction
• After reset
Condition for clearing (ACKEn = 0)
• Cleared by instruction
• After reset
ACKEn
WTIMn
SPIEn
0
1
0
1
0
1
Disabled
Enabled
Interrupt request is generated at the eighth clock’s falling edge.
Master mode: After output of eight clocks, clock output is set to low level and wait is set.
Slave mode: After input of eight clocks, the clock is set to low level and wait is set for the master
device.
In order to generate the ninth clock on SCLn the wait status must be cancelled by writing to IICn or
setting IICCn.WRELn = 1. Consequently the ninth clock will be delayed until the wait status is
cancelled.
Interrupt request is generated at the ninth clock’s falling edge.
Master mode: After output of nine clocks, clock output is set to low level and wait is set.
Slave mode: After input of nine clocks, the clock is set to low level and wait is set for the master
device.
Acknowledgment disabled.
Acknowledgment enabled. During the ninth clock period, the SDAn line is set to low level.
However, ACK is invalid in other than extension mode during address transfers.
Note
Note
Enable/disable generation of interrupt request when stop condition is detected
1.
2.
This flag’s signal is invalid when the IICEn = 0.
Preliminary User’s Manual U17566EE1V2UM00
The IICS register, IICFn.STCFn and IICFn.IICBSYn bits, and IICCLn.CLDn
and IICCLn.DADn bits are reset.
This flag’s signal is invalid when the IICEn = 0.
Note 2
Note
Note
Control of wait and interrupt request generation
Acknowledgement control
Condition for setting (SPIEn = 1)
• Set by instruction
Condition for setting (WTIMn = 1)
• Set by instruction
Condition for setting (ACKEn = 1)
• Set by instruction
Note
I
2
C Bus (IIC)