upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 142

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 4
142
Bit position
7
5
4
2
Insitial Value
Table 4-7
Address
Access
Bit name
SOSCP
MFRC
FRC
CLS
(5)
PCC - Processor clock control register
The 8-bit PCC register controls the CPU clock. This register can be changed
only once after reset or power save mode release.
This register can be read/written in 8-bit units.
Writing to this register is protected by a special sequence of instructions.
Please refer to “PHCMD - Command protection register” on page 140 for
details.
FFFF F828
10
a)
PCC register contents (1/2)
Preliminary User’s Manual U17566EE1V2UM00
H
FRC
R/W
Function
Sub oscillator circuit: Control of internal return resistance
Set FRC only to 1, if the sub oscillator is not used.
Main oscillator circuit: Control of internal return resistance
Do not change the initial setting. To ensure correct operation of the main oscillator,
the internal feed-back resistor must remain connected.
Processor clock source monitor flag:
It is not possible to set this bit to 1 by writing to the register.
On Sub-WATCH release, the CLS bit is set to the state of PSM.OSCDIS. This is the
only way to set CLS to 1, which means, the main oscillator remains stopped and the
CPU is supplied with the sub clock chosen by SOSCP.
CLS is automatically cleared when the processor clock source is changed by writing
to PCC.CKS[1:0].
If CLS is 1, the bits CKS[1:0] have no meaning.
Sub clock selection:
This setting takes effect when bit CLS is 1.
Caution:
. The register is initialized by any reset.
7
0: Resistor connected.
1: Resistor disconnected.
0: Resistor connected.
1: Resistor disconnected.
0: Main oscillator operation—source can be the output of main oscillator, PLL, or
1: Sub clock operation: 32 KHz sub or 240 KHz ring oscillator (selection through
0: ring oscillator is used for sub clock operation.
1: sub oscillator is used for sub clock operation.
These bits may be written, but write is ignored.
SSCG (selection through CKS[1:0]). The main oscillator is enabled by the
internal firmware.
bit SOSCP). This is the default after reset.
H
R
.
Do not specify the sub oscillator, if the sub oscillator is not enabled or
not connected.
6
0
a
MFRC
R/W
5
CLS
R
4
a
R
3
0
a
SOSCP
R/W
2
CKS1
R/W
Clock Generator
1
CKS0
R/W
0