upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 492

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 14
492
Initial Value
Initial Value
Address
Address
Access
Access
Note
(4)
(5)
CR000 - WCT capture / compare register 1
The 16-bit CR000 register can be used as a capture register or as a compare
register. Whether it is used as a capture register or compare register is
specified in bit CRC00.CRC000.
• Compare mode:
• Capture mode:
In compare mode, this register can be read/written in 16-bit units. In capture
mode, it cannot be written.
<base> + 4
0000
Stop the timer before changing the contents of this register.
TM00 - WCT timer / counter read register
The TM00 register can be used to read the present value of the 16-bit up-
counter.
The counter is increased with every rising edge of the input clock. If the
counter value is read while the counter is running, input of the count clock is
temporarily stopped, and the counter value at this point is read.
This register is read-only, in 16-bit units.
<base>
0000
(TMC00.TMC00[3:2] = 0), and when the counter is in INTWT0UV interval
measurement mode and a valid edge of INTWT0UV is detected.
When the counter overflows, it sets the flag TMC00.OVF00 to 1 and continues
with 0000
Preliminary User’s Manual U17566EE1V2UM00
15
15
In compare mode, the value written to CR000 is continually compared with
the count value of TM00. When the two values match, the interrupt request
INTTM00 is generated.
In capture mode, the count value of TM00 is copied to CR000 upon a valid
edge of INTWT0UV. Then, the interrupt INTTM00 is generated.
The valid edge of INTWT0UV can be selected as a capture trigger. The valid
edge is specified in PRM00.ES00[1:0].
In capture mode, a read access to register CR000 is not synchronized with
the counter operation. Read access and register update can occur
simultaneously. If that happens, CR000 holds the correct value, but the
value read is undefined.
H
H
14
14
. This register is cleared by any reset.
. This register is cleared by any reset, when the counter is stopped
H
.
13
13
H
12
12
Compare or captured value (captured from TM00)
11
11
10
10
9
9
Counter value
8
8
R(W)
R
7
7
6
6
5
5
4
4
Watch Timer (WT)
3
3
2
2
1
1
0
0