upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 499

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Watchdog Timer (WDT)
15.1.3 Watchdog Timer clock
Note
(2)
(3)
Watchdog Timer mode 1 (generate reset request RESWDT)
If WDTM.WDTMODE is 1, the Watchdog Timer is in reset-request mode.
Setting bit WDTM.RUN to 1 starts the counter. Without intervention, the timer
will now run until the specified time has elapsed and then generate the internal
RESWDT signal. After that, the counter operation is stopped until the system
reset SYSRES or SYSRESWDT occurs.
Watchdog Timer running
Once it is running, the Watchdog Timer cannot be stopped by software. It can
only be stopped by the reset signal SYSRESWDT. This signal is generated by
the Reset module at power-on and external RESET.
The way to prevent the timer from flowing over is writing to the register WDTM
before the specified time has elapsed. The write access resets the counter to
zero.
The Watchdog Timer clock WDTCLK is generated by the Clock Generator. It
can be derived from the main, ring or sub oscillator.
The generation of WDTCLK is controlled by the WCC register of the Clock
Generator.
In this register, it is possible to choose the main, sub, or ring oscillator as the
clock source (WCC.SOSCW, WCC.WDTSEL0).
You can also choose a suitable frequency divider between 1 and 128
(WCC.WPS[2:0]).
Please refer to “Clock Generator“ on page 129 for further details.
Once the timer has been started, do not switch off the selected clock source of
WDTCLK.
When the microcontroller is in HALT mode, the Watchdog Timer remains
active.
The activity in the other power save modes depends on the availability of the
WDTCLK clock source.
When the WDTCLK resumes operation, the Watchdog Timer is not reset but
continues counting. To prevent a quick and unexpected overflow, it is
recommended to write to WDTM and thus clear the Watchdog Timer counter
before entering one of these power save modes.
Preliminary User’s Manual U17566EE1V2UM00
Chapter 15
499