upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 514

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 16
a)
514
Bit position
4 to 2
Before starting the SBF transmission by UAnOPT0.UAnSTT = 1 make sure that no data transfer is ongoing,
that means check that UAnSTR.UAnTSF = 0.
7
6
5
1
0
Table 16-4
UAnSBL[2:0]
Bit name
UAnSRF
UAnSRT
UAnRDL
UAnSTT
UAnTDL
UAnOPT0 register contents
Preliminary User’s Manual U17566EE1V2UM00
Function
SBF reception flag:
• SBF (Sync Brake Field) reception is judged during LIN communication.
• The UAnSRF bit is held at 1 when an SBF reception error occurs, and then
SBF reception trigger:
• This is the SBF reception trigger bit during LIN communication, and when
• Set the UAnSRT bit after setting the UAnPWR bit = UAnRXE bit = 1.
SBF transmission trigger:
• This is the SBF transmission trigger bit during LIN communication, and when
• Set the UAnSTT bit after setting the UAnPWR bit = UAnTXE bit = 1.
SBF transmission length selection:
This register can be set when the UAnPWR bit = 0 or when the UAnTXE bit = 0.
Transmit data level bit
• The output level of the TXDAn pin can be inverted using the UAnTDL bit.
• This register can be set when the UAnPWR bit = 0 or when the UAnTXE bit =
Receive data level bit
• The output level of the RXDAn pin can be inverted using the UAnRDL bit.
• This register can be set when the UAnPWR bit = 0 or the UAnRXE bit = 0.
0: When the UAnCTL0.UAnPWR bit = UAnCTL0.UAnRXE bit = 0 are set.
1: During SBF reception
0: –
1: SBF reception trigger
0: –
1: SBF transmission trigger
0: Normal output of transfer data
1: Inverted output of transfer data
0: Normal input of transfer data
1: Inverted input of transfer data
SBF reception is started again.
read, “0” is always read. For SBF reception, set the UAnSRT bit (to 1) to
enable SBF reception.
read, “0” is always read.
0.
Also upon normal end of SBF reception.
UAnSBL2
1
1
1
0
0
0
0
1
UAnSBL1
0
1
1
0
0
1
1
0
a
UAnSBL0 SBF transmission length
Asynchronous Serial Interface (UARTA)
1
0
1
0
1
0
1
0
13-bit output (default value)
14-bit output
15-bit output
16-bit output
17-bit output
18-bit output
19-bit output
20-bit output