upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 197

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Interrupt Controller (INTC)
Caution
5.2 Non-Maskable Interrupts
(1)
(2)
A non-maskable interrupt request is acknowledged unconditionally, even when
interrupts are in the interrupt disabled (DI) status.
Non-maskable interrupts of this microcontroller are available for the following
two requests:
• NMI0: NMI pin input
• NMIWDT: Non-maskable Watchdog Timer interrupt request
When the valid edge specified by the ESEL0, ESEL00 and ESEL01 bits of the
Interrupt mode register 0(INTM0) is detected on the NMI pin, the interrupt
occurs.
The Watchdog Timer interrupt request is only effective as non-maskable
interrupt if the WDTMODE bit of the Watchdog Timer mode register (WDTM) is
set 0.
If multiple non-maskable interrupts are generated at the same time, the highest
priority servicing is executed according to the following priority order (the lower
priority interrupt is ignored):
Note that if a NMI from port pin or NMIWDT request is generated while NMI
from port pin is being serviced, the service is executed as follows.
If a NMI0 is generated while NMI0 is being serviced
The new NMI0 request is held pending regardless of the value of the PSW.NP
bit. The pending NMIVC request is acknowledged after servicing of the current
NMI0 request has finished (after execution of the RETI instruction).
If a NMIWDT request is generated while NMI0 is being serviced
If the PSW.NP bit remains set (1) while NMI0 is being serviced, the new
NMIWDT request is held pending. The pending NMIWDT request is
acknowledge after servicing of the current NMI0 request has finished (after
execution of the RETI instruction).
If the PSW.NP bit is cleared (0) while NMI0 is being serviced, the newly
generated NMIWDT request is executed (NMI0 servicing is halted).
1.
2.
Preliminary User’s Manual U17566EE1V2UM00
Although the values of the PC and PSW are saved to an NMI status save
register (FEPC, FEPSW) when a non-maskable interrupt request is
generated, only the NMI0 can be restored by the RETI instruction at this
time. Because NMIWDT cannot be restored by the RETI instruction, the
system must be reset after servicing this interrupt.
If PSW.NP is cleared to 0 by the LDSR instruction during non-maskable
interrupt servicing, a NMI0 interrupt afterwards cannot be acknowledged
correctly.
NMIWDT > NMI0
Chapter 5
197