upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 591

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

I
2
C Bus (IIC)
Clock Stretching
Figure 18-3
Heavy capacitive load and the dimension of the external pull-up resistor on the
I
SDAn. Since the controller senses the level of the I
such situation and takes countermeasures by stretching the clock SCLn in
order to ensure proper high level time t
After the microcontoller releases the (open-drain) SCLn pin it waits until the
SCLn level exceeds the valid high level threshold V
SCLn to low level before the nominal high level time t
This mechanism is the same used, when a slow I
down SCLn to low level to initiate a wait state.
Figure 18-3 shows an example.
Clock Stretching of SCLn
The effective clock frequency appearing at the SCLn pin calculates to
f
With a nominal frequency of f
rise time of t
Preliminary User’s Manual U17566EE1V2UM00
2
SCL_eff
C bus pins may yield extended rise times of the rising edge of SCLn and
effective SCL
= 1 / (T
SCL signal
clock
r
V
= 135 ns the effective frequency is f
thH
SCL_nom
t
r
+ t
r
)
SCL_nom
t
SCLH
T
SCL_nom
= 355 KHz (T
T
SCLH
SCL_eff
t
SCLL
of SCLn.
eff
2
2
C slave device is pulling
thH
C bus signals it recognizes
SCL_nom
t
= 339 KHz.
r
SCLH_nom
. Then it does not pull
= 2.817 µs and a
has elapsed.
Chapter 18
591