upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 653

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

CAN Controller (CAN)
<1>
<2>
<3>
<4>
<5>
No
Figure 19-16
Table 19-8
Name
Overload flag
Overload flag from other
node
Overload delimiter
Frame
Interframe space/overload
frame
19.2.5 Overload frame
R
D
Note
(<4>)
An overload frame is transmitted under the following conditions.
• When the receiving node has not completed the reception operation
• If a dominant level is detected at the first two bits during intermission
• If a dominant level is detected at the last bit (7th bit) of the end of frame or at
Overload frame
1.
2.
Definition of overload frame fields
Preliminary User’s Manual U17566EE1V2UM00
the last bit (8th bit) of the error delimiter/overload delimiter
6 bits
<1>
D: Dominant = 0
R: Recessive = 1
Node n ≠ node m
Overload frame
0 to 6 bits
<2>
count
0 to 6
Bit
6
8
–
–
8 bits
<3>
Definition
Outputs 6 dominant-level bits consecutively.
The node that received an overload flag in the interframe
space outputs an overload flag.
Outputs 8 recessive-level bits consecutively.
If a dominant level is detected at the 8th bit, an overload
frame is transmitted from the next bit.
Output following an end of frame, error delimiter, or
overload delimiter.
An interframe space or overload frame starts from here.
(<5>)
Interframe space or overload frame
Overload delimiter
Overload flag (node n)
Overload flag (node m)
Frame
Chapter 19
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