upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 486

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 14
486
Start-up timing
Figure 14-3
WT1CTL.WTCE=1
14.3.2 Watch Timer start-up
INTWT0UV
S/W counter
WT1 start
INTWT0UV
WT1R
The first interval after starting WT0 and WT1 until their first underflow takes at
least four additional input clock cycles. At this point in time, the values of the
counter registers WTnCNT are not correct.
After the first automatic reload of the WTnR value, the counter registers
WTnCNT hold the correct number of clock cycles since the last underflow.
In the following, the start-up procedure of WT1 is described, because of its
higher relevance from an application point of view. However, all statements
refer also to WT0.
Starting WT1 correctly requires some attention in order to avoid wrong
calculation of the watch time.
If WT1 is used as an extended Watch Timer counter, two steps in the following
order are required:
• The counter has to be enabled by setting WT1CTL.WTCE = 1.
• The counter's reload register WT1R has to be set to a non-zero value.
Both actions consume a different amount of input clock cycles to become
effective, as shown in the following diagram.
WT1 start-up timing
To start the counter in a deterministic way, the above actions have to be
synchronized to the WT1 input clock, which is INTWT0UV. For that purpose it
is recommended to maintain a software counter that is increased inside the
INTWT0UV interrupt service routine. By this means, it is ensured that the
actions are performed at the correct point in time.
Setting WT1CTL.WTCE to 1 enables WT1. The write access can happen at
any time. Due to internal clock synchronization, it takes at least two complete
input clock cycles, that means two INTWT0UV intervals (WTCE validation time
0 –> 1 –> 2) to become effective. After that, WT1 is prepared to acknowledge
the reload value.
S/W counter state “2” indicates that the reload value can be written now
(WT1R > 0). This time, at least three complete input clock cycles (WTR1
validation time 3 –> 4 –> 5 –> 6) are required to take over the reload value from
WT1R to the reload buffer and to start counting. At S/W counter state 6 the
counter WT1CNT is preloaded with the WT1R contents.
Preliminary User’s Manual U17566EE1V2UM00
0
WT1R = 0
validation
WTCE
1
2
stopped
WT1R > 0
3
4
validation
WT1R
5
6
started
Watch Timer (WT)
7