upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 126

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 3
126
Instruction
execution
3.7 Instructions and Data Access Times
The below Table 3-16 and Table 3-17 list the instruction execution and data
access cycles, required when accessing instructions or data in VFB
flash/ROM, and VDB RAM and VSB flash/RAM.
The access time depends on the
• memory type (flash, ROM, RAM) and access bus (VFB, VDB, VSB)
• number of latency cycles for the memory type
• type of data (instructions/data)
• type of access (consecutive/random addresses)
• device, i.e. maximum clock frequency
In general the CPU is able to execute most instructions in one clock cycle
(single-cycle instructions), provided no additional clock cycles are required to
access the memory.
Note that for some instructions the CPU requires more clock cycles to execute
anyway (multi-cycle instructions), regardless of the memory access time.
The memory access time in a real application is deterministic, but can hardly
be predicted, as this heavily depends on the status of the microcontroller and
its components, the program flow and concurrent processes, like DMA
transfers, interrupts, accesses to peripheral registers via the NPB, etc.
Thus the figures in the below tables assume
• all busses (VFB, VDB, VSB, NPB) are not occupied, i.e. collision with other
• 32-bit instruction/data accesses to word-aligned - that means 32-bit
• data is not accessed via the same bus as the instruction is fetched from
Consequently “1 clock cycle” means: the instruction/data access takes one
CPU clock cycle and the CPU is supplied with an instruction/data in each
clock: the memory access time is invisible and has no effect.
The given numbers of cycles in Table 3-16 describe the time required to
execute a single-cycle instruction, fetched from the respective memory:
• Consecutive access
• Random access
In case instructions and data are accessed via the same bus, all accesses -
Preliminary User’s Manual U17566EE1V2UM00
instruction fetch and data access - are regarded as random accesses.
bus traffic is excluded
aligned - addresses
describes the number of cycles required to fetch instructions from the
memory on consecutive addresses.
describes the number of cycles required to access the memory in case
instructions are accessed on random, i.e. non-consecutive, addresses. In
case of instruction flow branches a CPU’s pipeline break occurs and an
additional cycle is required to refill the pipeline. The table figures include
this cycle.
CPU System Functions