upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 587
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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I
2
Condition for clearing (IICRSVn = 0)
• Clearing by instruction
• After reset
C Bus (IIC)
IICRSVn
0
1
Communication reservation enabled
Communication reservation disabled
Caution
Note
Bits 6 and 7 are read-only bits.
1.
2.
3.
Preliminary User’s Manual U17566EE1V2UM00
Write the STCENn bit only when operation is stopped
(IICEn = 0).
When the STCENn = 1, the bus released status (IICBSYn = 0) is recognized
regardless of the actual bus status immediately after the I
is enabled. Therefore, to issue the first start condition (STTn = 1), it is
necessary to confirm that the bus has been released, so as to not disturb
other communications.
Write the IICRSVn bit only when operation is stopped (IICEn = 0).
Communication reservation function disable bit
Condition for setting (IICRSVn = 1)
• Setting by instruction
2
Cn bus operation
Chapter 18
587
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