upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 377

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

16-bit Timer/Event Counter P (TMP)
External trigger input
INTTPnCC1 signal
INTTPnCC0 signal
TPnCCR0 register
TPnCCR1 register
TOPn0 pin output
TOPn1 pin output
(software trigger)
(TIPn0 pin input)
Figure 11-15
16-bit counter
TPnCE bit
FFFFH
0000H
Basic timing in external trigger pulse output mode
16-bit timer/event counter P waits for a trigger when the TPnCE bit is set to 1.
When the trigger is generated, the 16-bit counter is cleared from FFFFH to
0000H, starts counting at the same time, and outputs a PWM waveform from
the TOPn1 pin.
If the trigger is generated again while the counter is operating, the counter is
cleared to 0000H and restarted.
The active level width, cycle, and duty factor of the PWM waveform can be
calculated as follows.
The compare match request signal INTTPnCC0 is generated when the 16-bit
counter counts next time after its count value matches the value of the CCR0
buffer register, and the 16-bit counter is cleared to 0000H. The compare match
interrupt request signal INTTPnCC1 is generated when the count value of the
16-bit counter matches the value of the CCR1 buffer register.
The value set to the TPnCCRm register is transferred to the CCRm buffer
register when the count value of the 16-bit counter matches the value of the
CCRm buffer register and the 16-bit counter is cleared to 0000H.
The valid edge of an external trigger input signal, or setting the software trigger
(TPnCTL1.TPnEST bit) to 1 is used as the trigger.
Preliminary User’s Manual U17566EE1V2UM00
trigger
Wait
for
Active level width = (Set value of TPnCCR1 register) × Count clock cycle
Cycle = (Set value of TPnCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TPnCCR1 register)/(Set value of TPnCCR0 register + 1)
Active level
width (D
Cycle (D
D
1
1
)
D
0
0
+ 1)
Active level
width (D
Cycle (D
D
1
1
)
D
0
0
+ 1)
D
D
0
1
D
1
D
0
Active level
width (D
Cycle (D
D
1
1
)
D
0
0
+ 1)
Chapter 11
377