upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 451

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

16-bit Multi-Purpose Timer G (TMG)
Match and
CCSGn5
Free-run
mode
mode
clear
0
1
Register setting value
Table 13-9
TBGnm
1
13.7 Operation in Free-Run Mode
Note
(1)
SWFGnm
Interrupt output and timer output states dependent on the register
setting values
0
1
0
1
1.
2.
3.
This operation mode is the standard mode for Timer Gn operations. In this
mode the 2 counter TMGn0 and TMGn1 are counting up from 0000H to
FFFFH, generates an overflow and start again. In the match and clear mode,
which is described in Chapter 13.8 on page 462 the fixed assigned register
GCCn0 (GCCn5) is used to reduce the bit-size of the counter TMGn0
(TMGn1).
Capture operation (free run)
Basic settings:
Preliminary User’s Manual U17566EE1V2UM00
An interrupt is generated only when the value of the GCCn5 register is
FFFFH.
An interrupt is generated only when the value of the GCCn5 register is not
FFFFH.
The setting of the CCSGnm bit in combination with the SWFGnm bit sets
the mode for the timing of the actualization of new compare values.
•
•
In compare mode the new compare value will be immediately active.
In PWM mode the new compare value will be active first after the next
overflow or match & clear of the assigned counter (TMGn0, TMGn1).
CCSGnm
SWFGnm
CCSGn0
CCSGn5
TBGnm
0
1
0
1
0
1
0
1
Bit
interrupt
INTTMGn1
Overflow
Overflow
interrupt
Note 1
match
INTCCGn5
detection
TI5 edge
GCCn5
State of each output pin
Value
Note 2
X
0
0
0
CMPGm match
CMPGm match
GCCnm match
GCCnm match
INTCCGnm
TIm edge
TIm edge
TIm edge
TIm edge
detection
detection
detection
detection
Remark
free run mode
disable TOGnm
assign counter
for GCCnm
0: TMGn0
1: TMGn1
(match and clear)
Tied to inactive
Tied to inactive
(free run)
TOGnm
Chapter 13
PWM
PWM
level
level
451