upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 316

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

DBC0
DBC1
DBC2
DBC3
Chapter 8
316
Bit position
15 to 0
BC15
BC15
BC15
BC15
15
15
15
15
BC14
BC14
BC14
BC14
14
14
14
14
BC13
BC13
BC13
BC13
Bit name
8.3.3 DBCn - DMA transfer count registers
13
13
13
13
BC15 to
BC0
BC12
BC12
BC12
BC12
12
12
12
12
These 16-bit registers are used to set the transfer counts for DMA channels n.
They store the remaining transfer counts during DMA transfer.
Since these registers are configured as 2-stage FIFO buffer registers, a new
DMA transfer count for DMA transfer can be specified during DMA transfer
(refer to “Automatic Restart Function” on page 323).
During DMA transfer these registers are decremented by 1 for each transfer
that is performed. DMA transfer is terminated when an underflow occurs (from
0 to FFFFH). On terminal count these registers are rewritten with the value that
was set to the DBCn master register before.
These registers can be read/written in 16-bit units.
Preliminary User’s Manual U17566EE1V2UM00
BC11
BC11
BC11
BC11
11
11
11
11
Function
Sets the transfer count. It stores the remaining transfer count during DMA transfer.
BC10
BC10
BC10
BC10
10
10
10
10
FFFFH
0000H
0001H
DBCn
BC9
BC9
BC9
BC9
:
9
9
9
9
BC8
BC8
BC8
BC8
8
8
8
8
States
Transfer count 1 or remaining transfer count
Transfer count 2 or remaining transfer count
Transfer count 65,536 (2
BC7
BC7
BC7
BC7
7
7
7
7
BC6
BC6
BC6
BC6
6
6
6
6
BC5
BC5
BC5
BC5
5
5
5
5
BC4
BC4
BC4
BC4
4
4
4
4
BC3
BC3
BC3
BC3
16
3
3
3
3
) or remaining transfer count
B2C
B2C
B2C
B2C
:
2
2
2
2
DMA Controller (DMAC)
BC1
BC1
BC1
BC1
1
1
1
1
BC0
BC0
BC0
BC0
0
0
0
0
FFFFF0C0H
FFFFF0C2H
FFFFF0C4H
FFFFF0C6H
Address
Address
Address
Address
undef.
undef.
undef.
undef.
value
value
value
value
Initial
Initial
Initial
Initial